This invention relates to the metallization of via and trench structures on semiconductor wafers. More particularly, the invention relates to the metallization of high aspect ratio via and trench structures of silicon wafers utilizing ionized sputtered materials to form the barrier and seed layers.
In the metallization of high aspect ratio via holes and trenches on semiconductor wafers it is required that the barrier layer and the seed layer have good sidewall and bottom coverage. The barrier layer needs to be as thin as possible without sacrificing its barrier properties. The barrier layer must be thin because its electrical resistance, which adds to the electrical resistance of the via structure, must be minimized. It needs to be conformal and continuous to prevent diffusion of seed layer material into the dielectric layer and into other layers to prevent reliability problems. This requires that the barrier layer thickness must be well controlled and minimized especially at the bottom of the via. A thick barrier layer at the bottom of the via may add substantial undesirable electrical resistance to the resistance of interconnect metallization. High contact resistance results in inferior IC performance. During barrier layer deposition, at the top edges of the via""s entrance, an overhang may form due to buildup of thicker material there. This overhang interferes with the deposition of the seed layer onto the sidewalls and the bottom of the via. During seed layer deposition, further overhang formation by the seed layer material itself must be prevented.
The seed layer must be continuous and have good coverage at the sidewalls and at the bottom of the vias. This is essential for the electroplating step which follows the barrier and seed layer deposition. The closure of the via entrance by overhang results in poor sidewall coverage, poor electroplated fill and low device yields.
Ionized PVD deposition is used for barrier and seed layer metallization in advanced IC wafers. Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, as the geometries shrink and as the via dimensions go down below 0.15 micrometers, ionized deposition requirements become more critical. Therefore, it is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized.
Sequential deposition and etch processes have been proposed previously. In U.S. Pat. No. 6,100,200, Van Buskirk, et al., teach a sequentially performed heated deposition and etch unit process to provide conformal coverage of via or trench structures. However, they teach deposition and etch processes at high substrate temperatures between 300xc2x0-600xc2x0 C. and 500xc2x0-450xc2x0 C. typically. Unfortunately, the new state-of-the-art low-k dielectrics that are used in current semiconductor processes require temperatures  less than 200xc2x0 C. Cu seed layer deposition requires  less than 0xc2x0 C., typically xe2x88x9220xc2x0 C. to xe2x88x9250xc2x0 C. to prevent copper agglomeration. The temperatures taught by Van Buskirk, et al., would result in total agglomeration of Cu seed layers, overhang and closure of via and trenches with large islands of Cu and discontinuous Cu layers. Van Buskirk, et al., also teaches low power sputtering typically less than 1 kW and particularly less than 0.5 kW. This puts severe deposition rate and throughput limitations on the process.
Furthermore, Van Buskirk, et al., teach sequential deposition and etching steps to be carried out in a singular vacuum system by transporting the wafer between dedicated deposition and etch modules, or in a singular vacuum system using a multi-faceted deposition and reactive ion etch module. Alternatively, Van Buskirk et al. suggests the steps may be carried out in independent deposition and etch systems. Transferring the wafer from one etch chamber to another deposition chamber or from an etch station to another deposition station within the same module has disadvantages both from cost of process and quality of process points of view. By transferring wafers from chamber to chamber or from one station to another station in the same chamber, loss of throughput results, and thus a more costly process. Some processes are sensitive to adsorption of gas molecules or other contaminants during transfer, which may be detrimental to the quality and reliability of the devices under construction. Another suggestion of Van Buskirk, et al., is to carry out the deposition and etch steps in independent systems with exposure to atmosphere in between processes, is totally unacceptable in most of the modern barrier/seed layer metallization processes. Van Buskirk, et al., also do not teach any substrate bias during the deposition step.
In U.S. Pat. No. 4,999,096, Nikei, et al., teach a method of and apparatus for sputtering when sequential deposition and etching in the same chamber can be performed. Nikei, et al., applies a negative voltage alternatively to a target and a substrate to perform film deposition and reverse sputter alternately. They teach an RF coil internal to the process module, situated between the target and substrate, to cause plasma generation for the etch step. This configuration has a significant disadvantage in that the internal coil is a source of contamination because it is well known in the art that energetic ions and neutrals that exist in the process space will also remove material from, i.e., etch, the coils and contaminate the film being deposited or etched on the substrate. In other prior art, the coil can be made from the same material that is being deposited, but this creates undue economic and hardware difficulties for the process. Not every material to be deposited is amenable to construct a coil and most of the time the cost is prohibitive. Furthermore, the suggestions of Nikei, et al., will result in non-uniform plasma generation and non-uniform etching of the substrate. It is essential in a sequential etching and deposition process that both steps be uniform across the wafer to result in a uniformly processed wafer at the end of the process.
Nikei, et al., strictly teach and emphasize a low pressure deposition and etching process to prevent impurity inclusion in the deposited films. This is achieved by creating the plasma at low pressure, such as on the order of 10xe2x88x923 torr or less during the etch and deposition process. During the etch process the internal coil needs to be RF powered to achieve a discharge which, contrary to their desire to keep certain contaminants from the substrate, now contributes contaminants to the substrate. Nikei, et al., strictly teach or limit their invention to low pressure (10xe2x88x923 torr or less) operation.
U.S. Pat. No. 6,274,008 teaches an integrated copper fill process where a simultaneous clean-deposit step is carried out. This invention uses copper ions to clean and/or etch the bottom of via structures before the copper seed layer is deposited.
According to principles of the present invention, a process and an apparatus are provided wherein sequential deposition and etching steps are used to solve the problems set forth above. The process of the invention involves first depositing a thin layer of metallization, for example, tantalum (Ta), tantalum nitride (TaN) or copper (Cu), and then, preferably after stopping the deposition, performing an ion etch step, preferably by ionized gas, for example, argon (Ar).
The etching step removes less material on both the field area on the top surface of the wafer and the via bottom than is deposited during the deposition step, and thus there is net deposition at the end of the process cycle. The deposition/etch cycle can be repeated as many times as needed to achieve the desired result. By balancing the deposition and etching times, rates and other deposition and etch parameters, the overhang growth is eliminated or minimized. The overhang and bottom deposition is etched back and redistributed at least partially to the sidewalls.
In the process according to one embodiment of the invention, material is deposited onto a wafer having small high aspect ratio features, for example, holes or vias of diameters of 0.15 micrometers or less with aspect ratios of from three or five, to fifteen or higher. The deposition uses an ionized physical vapor deposition (iPVD) process and apparatus having the features as described in U.S. Pat. Nos. 6,287,435, 6,080,287, 6,197,165, 6,132,564, 5,948,215 and 5,800,688, and PCT application PCT/US00/31756 based at least in part thereon, all hereby expressly incorporated by reference herein.
One embodiment of the invention utilizes the unique advantages of the ionized PVD apparatus as described in more detail in connection with FIG. 1 of U.S. Pat. No. 6,287,435 and PCT application PCT/US00/31756 referred to above. This apparatus is particularly well suited for the sequential deposition and etching process. The sequential deposition and etching process can be applied to a substrate in the same process chamber without breaking vacuum or moving the wafer from chamber to chamber. The configuration of the apparatus allows rapid change from ionized PVD deposition mode to etching mode or from etching mode to ionized PVD deposition mode. The configuration of the apparatus also allows for instantaneous optimization of ionized PVD deposition process control parameters during deposition mode and etching process control parameters during etching mode. The consequence of these advantages is a high throughput of wafers with superior via metallization and subsequent electroplated fill operation.
The invention, in addition to teaching low substrate temperature, proposes high DC target power, for example 8 kW to 19 kW, typically 11 kW. The high power levels not only result in a high throughput process but also optimize the ionization and ionized deposition of the metallic species, such as Cu or Ta.
The invention solves problems of the prior art by providing the sequential etch and deposition steps in situ in the same chamber with high throughput and without interfacial layers that may develop in the processes taught by Van Buskirk, et al.
The configuration of the process module provided by the present invention accommodates a wide range of pressures to result in conformal via and trench coverage at high wafer throughput levels. The invention does not have the low pressure limitations of Nikei, et al., and provides process pressure levels optimized for sputtering and etching steps of the process utilizing capabilities of the apparatus. Furthermore, the prior art does not teach a deposition-etch cycle with optimized source-to-substrate distance for each step to increase the uniformity of the resulting films.
U.S. Pat. No. 6,274,008 does not teach a sequential etch and deposit scheme and is limited to metal ions as the cleaning species.
These and other objects and advantages of the present invention will be more readily apparent from the following detailed description of illustrated embodiments of the invention.